1. Field of the Invention
The invention relates to semiconductor memories, and in particular to a method and apparatus for testing the integrity of memory storing controlled information.
2. Art Background
In semiconductor memories, such as static and dynamic random-access memories (RAMs), predetermined data patterns are used to test the memory for defects. In general, data patterns such as checkerboard, complement of checkerboard, walking 1's, walking 0's, crossing 1's or crossing 0's are written and read from each array of memory and compared with the expected values. However, for memories that store controlled information such as, an instruction cache or a programmable random read only memory (PROM) used on-chip with a central processor unit (CPU), or Microcode ROM; the prior art method of testing memory is unworkable because the binary patterns from such memory that stores controlled information means something other than the binary numbers. Furthermore, for normal operation of an instruction cache, there is no need to write into the instruction cache. The instructions are brought in during the instruction cache miss during replace cycles and then read by the integer execution unit or the floating point control units. The integer execution unit or the floating point control unit does not write into the instruction cache directly. As such, extra hardware is required to allow the writing by the integer execution unit into the instruction cache for testing the instruction cache.
Another problem related to the testing of instruction cache is that it requires a special mode which permits the simultaneous reading of the test pattern from the instruction cache and bypassing the instruction cache. This arises because the integer execution unit requires instruction for generating control for handling test pattern reading and performing comparison functions at the same time. The special mode with dedicated hardware is needed to accomplish this testing function. Over-all, the cost of extra hardware and special mode logic complexity needed for testing memory that stores controlled information is significant.
It is therefore an object of the present invention to provide a method and apparatus for testing the memory storing controlled information with minimal hardware overhead and simple software instructions.
It is yet another object of the present invention to partition the memory array into two halves and be able to load instruction in one half and test pattern into the other half in performing a testing of the memory with minimal hardware.
It is yet another object of the present invention to swap one-half of a memory array divided into two halves and compare the other half with an expected value in testing the integrity of the memory.